Pranay Kotasthane quoted in CNBC on Huawei’s chip design tools

Pranay Kotasthane, Deputy Director and Chairperson - High Tech Geopolitics Programme at Takshashila, was quoted in CNBC on Huawei’s claims of having developed chip design tools. He was quoted as saying:

Pranay Kotasthane, chairperson of the high tech geopolitics program at the Takshashila Institution, told CNBC he would wait to see more details before knowing how effective Huawei’s design tools are.

Kotasthane explained that contract chip manufacturing firms, also known as foundries, work with semiconductor design companies to come up with a set of files called a Process Design Kit. This PDK “models the physical and electrical characteristics” of the basic components of a chip. The design firm and manufacturer needs to go through a process to optimize the production to ensure the highest yield of semiconductors. If this process does not happen, then “chip designs will fail when converted into silicon,” Kotasthane said.

“There’s not enough proof yet to suggest that Chinese EDA [electronic design automation] companies have crossed this barrier,” Kotasthane said.

Read the full report here.